The present invention relates to a driver circuit for driving a motor or the like.
Japanese Laid-Open Patent Publication No. 2005-354586 (page 1 and FIG. 1) describes a driver circuit for driving a motor or the like. Such a driver circuit may have a full or half bridge connection. The driver circuit of Japanese Laid-Open Patent Publication No. 2005-354586 lowers power consumption. In this publication, the driver circuit includes high and low side MOS transistors. A connection node between the high and low side MOS transistors serves as an output terminal of the driver circuit. The high side MOS transistor has a top gate connected to a pre-driver circuit. The pre-driver circuit includes an input terminal and a constant current source connected to the top gate. The pre-driver circuit drives the constant current source in accordance with the signal received by the input terminal. When the high side MOS transistor is activated, the voltage generated by the charge stored in a parasitic capacitance is added to the voltage at the connection node and applied to the top gate.
One type of a pre-driver circuit drives the high side transistor while monitoring the output voltage. When the gate-source withstand voltage of a high side transistor is low in a motor driver circuit, the source voltage must be monitored when applying a control voltage to the gate. Such a driver circuit DC1 will now be described with reference to FIGS. 3 and 4.
The driver circuit DC1 supplies power to a motor M1. The driver circuit DC1 includes a pre-driver 10 and a motor driver 11.
The motor driver 11 includes a high side transistor 111 and a low side transistor 112. The drain of the high side transistor 111 is supplied with voltage V1. The source of the high side transistor 111 is connected to the drain of the low side transistor 112. The source of the low side transistor 112 is connected to ground.
An external terminal TM1 is arranged at a connection node between the source of the high side transistor 111 and the drain of the low side transistor 112. Voltage V2 is supplied from the external terminal TM1 to the motor M1. The gate of the high side transistor 111 is supplied with a high side control voltage V5 from the pre-driver 10. The voltage V2 at the external terminal TM1 is fed back to the pre-driver 10 and used for voltage monitoring.
The pre-driver 10 includes buffers 12, 13, and 14, transistors 131 to 138, a resistor 15, and a regulator 16. The pre-driver 10 obtains an input signal S1, which controls the motor driver 11. An inverted signal S2 of the input signal S1 is provided to the buffer 13 and then to the gate of the transistor 112.
The regulator 16 obtains the voltage V2 via the resistor 15. The regulator 16 increases the voltage V2 to voltage V4, which is for driving the transistors 131 to 138. The gate of the transistor 131 is connected to the drain of the transistor 132. The gate of the transistor 132 is connected to the drain of the transistor 131. Further, the drains of the transistors 131 and 132 are respectively connected to the sources of the transistors 133 and 134. The drain of the transistor 132 is further connected to the input terminal of the buffer 12 to supply a converted voltage of the input signal S1. The gates of the transistors 133 and 134 are connected to the external terminal TM1 via the resistor 15. Further, the drains of the transistors 133 and 134 are respectively connected to the drains of the transistors 135 and 136. The gates of the transistors 135 and 136 are supplied with a voltage V3. The sources of the transistors 135 and 136 are respectively connected to the drains of the transistors 137 and 138.
The input signal S1, which is provided from an external device, is provided to the buffer 14, which is driven by the voltage V3, and the gate of the transistor 137. The buffer 14 provides the transistor 138 with an inverted signal of the input signal S1. The sources of the transistors 137 and 138 are connected to a ground line.
The operation of the driver circuit DC1 will now be discussed with reference to FIGS. 4A to 4B. Here, a simulation was performed by generating the input signal S1 and a load current I2. FIG. 4A is a timing chart of the input signal S1. The input signal S1 shifts to a high level at times t11 to t13 and t15 to t17. FIG. 4B illustrates the generation of the load current I2. When the load current I2 is positive, current is supplied from the driver circuit DC1 to the motor M1. When the load current I2 is negative, the motor M1 generates back electromotive force (EMF), which reverses the load current I2.
When the input signal S1 is high, the transistor 137 is activated, and the transistor 138 is deactivated. In this case, the source of the transistor 135 is at ground level. Thus, the transistor 135 is activated.
The transistors 133 and 134 form a clamp circuit, which protects the gates of the transistors 131 and 132. The source of the clamp circuit (i.e., the sources of the transistors 133 and 134) functions to keep the voltage above the sum of the voltage V2 and a threshold voltage Vt (voltage V2+threshold voltage Vt). Accordingly, the gate-source voltage at the gates of the transistors 131 and 132 does not exceed the maximum tolerable voltage (MaxVgs).
The transistors 135 and 136 form a clamp circuit that protects the transistors 137 and 138 by preventing the drain voltage of the transistors 137 and 138 from exceeding the voltage V3. The source of the clamp circuit (i.e., the sources of the transistors 135 and 136) functions to keep the voltage below the difference of the voltage V3 and the threshold voltage Vt (voltage V3−threshold voltage Vt). Accordingly, the drain-source voltage of the transistors 137 and 138 does not exceed the maximum tolerable voltage (MaxVgs).
When the voltage V2 is low, the voltage at the source of the transistor 133 (i.e., the gate of the transistor 132) is low. Thus, the transistor 132 is activated. In this case, the gate of the transistor 131 is supplied with the voltage V4 via the drain of the transistor 132. Thus, the transistor 131 is deactivated. Further, the voltage at the drain of the transistor 132 is supplied to the buffer 12.
The buffer 12 supplies the high side control voltage V5 to the gate of the transistor 111. This activates the transistor 111. As a result, the voltage V1 is supplied to the motor M1. As shown in FIG. 4C, the high side control voltage V5 rises after a relatively short time delay D11.
When the input signal S1 has a low level, the transistor 138 is activated, and the transistor 137 is deactivated. In this case, the source of the transistor 136 is at ground level. Thus, the transistor 136 is activated. In this state, the drain of the transistor 134 is at ground level, and the source is clamped at the sum of the voltage V2 and the threshold voltage Vt (voltage V2+threshold voltage Vt). Further, the drain of the transistor 132 becomes equal to the sum of the voltage V2 and the threshold voltage Vt (voltage V2+threshold voltage Vt), and the input terminal of the buffer 12 goes low. Accordingly, the high side control voltage V5 supplied to the gate of the transistor 111 also goes low. This deactivates the transistor 111 and stops the supply of voltage V1 to the motor M1. In this case, the voltage at the gate of the transistor 131 goes low, the transistor 131 is activated, and the transistor 132 is deactivated.
Back EMF may be generated in the motor M1 thereby reversing the flow of current from the motor M1. In FIG. 4A, the load current I2 is negative at time t15. In this case, current is supplied from the external terminal TM1. Most of the reversed current flows through a body diode of the transistor 111 but some of the reversed current is returned to the pre-driver 10.
The current is supplied to the buffer 12 and the regulator 16. In such a case, the buffer 12 can't output a high signal. Thus, the buffer 12 cannot supply the high side control voltage V5 in correspondence with the input signal S1. Further, when the back EMF and reversed current are eliminated, the voltage V2 goes low. This activates the transistors 133 and 134 and supplies the voltage corresponding to the input signal S1. Thus, after the EMF is eliminated and the load current I2 becomes positive as shown in FIG. 4B, the high side control voltage V5 rises following a relative long time delay D12 as shown in FIG. 4C.
In this case, when the back EMF is eliminated, the transistor 111 is not activated. Thus, the motor driver 11 cannot supply power. This produces a glitch G1 as shown in FIG. 4D. Then, the transistor 111 is activated, and the voltage V2 is recovered.